Low Power Delay Product 10T Adder Circuit
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چکیده
In this paper, the various low power delay product full adder circuits have been analyzed. The adder is the fundamental blocks of any arithmetic circuit, so even a small reduction power or delay leads to improved performance of the circuit with optimal power saving. A 10T adder technique is the famous low power delay product full adder circuits with minimum transistor count. A new 10T technique based low power delay product full adder circuits have been proposed. To analyze the performance of proposed adder; the CMOS adder, 10T adder and proposed 10T adder are simulated using tanner EDA tools with 45nm technology. The power consumption in various sources and delay have been computed and analyzed for different supply voltage. Also power delay product and number of transistors for each design has been calculated and compared with other design. when VDD=1v, compared to Conventional CMOS the proposed 10T adder achieves power savings of 66.65%, PDP savings of 54.9% and area saving of 64% with the increased delay of 26%. It is also observed that compared to10T adder the proposed 10T adder achieves power savings of 36.11%, PDP savings of 50.69% and delay savings of 22.81%.
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